NewsMacroPolyU's Quantum-Tunnelling Transistor Breaks the Boltzmann Limit, Paving the Way for Energy-Efficient AI Chips

PolyU's Quantum-Tunnelling Transistor Breaks the Boltzmann Limit, Paving the Way for Energy-Efficient AI Chips

Author: Citybuzzยท

Key Takeaways

  • โ€ขA PolyU-led team published a quantum-tunnelling TFET in the journal Science that breaks the 60 mV per decade Boltzmann limit on transistor switching.
  • โ€ขThe device is built from a heterostructure of 2D bismuth and indium selenide layers, converting normally semi-metallic bismuth into a semiconductor to enable efficient quantum tunnelling.
  • โ€ขThe transistor operates at room temperature on silicon substrates and needs a gate-voltage range of just 160 mV, compared with 800 mV for conventional devices.
  • โ€ขThe device achieves both a high output current and an exceptional ON/OFF switching ratio, allowing it to drive multiple downstream logic gates with reduced circuit delays.
  • โ€ขThe research was a collaboration with the National University of Singapore, HKUST, Peking University, and the Singapore University of Technology and Design.
PolyU's Quantum-Tunnelling Transistor Breaks the Boltzmann Limit, Paving the Way for Energy-Efficient AI Chips

A research team at The Hong Kong Polytechnic University (PolyU) has engineered a novel tunnelling field-effect transistor (TFET) that breaks through the long-standing physical barrier known as the 'Boltzmann limit,' a significant advancement for microelectronics. Published in the journal Science, the breakthrough could reshape energy-efficient computing and the development of next-generation AI chips.

Conventional transistors, the building blocks of integrated circuits, rely on thermionic emission to switch on and off. At room temperature, this process requires a minimum gate voltage of 60 millivolts (mV), a constraint set by the Boltzmann limit that has hindered further miniaturization and energy-efficiency gains in high-performance electronics. The PolyU team, led by Prof. Jianhua Hao, Head of the Department of Physics and Materials and Chair Professor of Materials Physics and Devices, circumvented this limitation using quantum tunnelling.

Quantum tunnelling allows charge carriers to pass through an energy barrier that would be insurmountable under classical physics. By carefully engineering a heterostructure of 2D bismuth and indium selenide layers, the team transformed the normally semi-metallic bismuth into a semiconductor. This structural change enables efficient quantum tunnelling of carriers into the indium selenide, producing a transistor with subthreshold swing (SS) values well below the 60 mV per decade limit. The subthreshold swing measures how sharply a transistor switches between its OFF and ON states; a steeper switch means less voltage, and therefore less energy, is needed for each switching operation. The search for devices that beat this 60 mV/decade floor has been a long-standing goal in the field, with TFETs among the leading candidates studied worldwide alongside other steep-slope approaches such as negative-capacitance transistors.

The new TFET operates at room temperature on silicon substrates, a crucial practical advantage for integration into existing manufacturing processes. It requires a gate-voltage range of only 160 mV, compared with the 800 mV needed by conventional devices. This dramatic reduction in voltage requirements translates into significantly lower power consumption, a key factor for energy-efficient computing and for AI technology, which demands massive computational power. Because transistor switching energy scales with voltage, lowering operating voltages is one of the most direct levers for cutting the power draw of processors, an increasingly pressing concern as the compute and energy requirements of AI training and inference continue to grow.

A major challenge in previous experimental TFETs was achieving a high output current while maintaining a high ON/OFF current ratio. The PolyU device overcomes this hurdle, delivering both a high output current and an exceptional ON/OFF switching ratio. This performance allows the transistor to drive multiple downstream logic gates and reduces circuit delays, making it suitable for practical integrated circuits.

Prof. Hao emphasized the significance of the work: 'By adopting quantum tunnelling, our TFET breaks through this boundary, paving the way for ultra-low-power, high-performance integrated circuits essential for emerging AI chips and advanced semiconductor applications.'

The research was conducted in collaboration with the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design.

The development carries broad implications for the future of electronics. As the semiconductor industry approaches the physical limits of conventional MOSFET technology, innovative approaches such as quantum-tunnelling TFETs offer a viable path forward. Operating at lower voltages without sacrificing performance could enable more efficient data centers, longer battery life in mobile devices, and more powerful AI systems that consume less energy. The successful demonstration of the technology on silicon substrates suggests a smoother transition from research to commercial application, though moving from a laboratory demonstration to volume manufacturing typically requires further development in materials quality, device uniformity, and large-scale process integration.

Source: Citybuzz