A senior Google executive has reportedly confirmed that the company has found a workaround to the AI-driven memory chip supply crunch and price increases that have stalled the entire tech sector: recycling DDR4 memory pulled from retired servers and installing it in its newest AI machines.

Nikhil Cherian, senior director of supply chain infrastructure, said that even with the DDR4 recycling pivot, the tech giant is still struggling to source enough chips for its AI systems. In his view, the only lasting solution to the extremely tight supply situation is for memory makers to build more capacity — and quickly.

The squeeze stems from the way AI systems consume memory: training and inference require far more memory bandwidth and capacity per server than conventional cloud workloads, and manufacturers have been shifting production toward high-bandwidth memory (HBM) for AI accelerators, leaving less capacity for conventional DRAM.

Firms are now reusing old memory chips

Google is not alone in searching for ways to avoid AI accelerators that cost billions of dollars to build sitting idle while companies haggle over per-module pricing for scarce memory bandwidth.

Meta laid out its own approach to recycling DDR4 in a paper published earlier this year, built on Compute Express Link (CXL), an industry-standard interconnect that pools older DDR4 and newer DDR5 within a single machine so that legacy modules can serve as expansion memory rather than being scrapped.

Khurram Malik, Marvell's associate vice president of product marketing, told EE Times that hyperscalers are finding ways to prolong the shelf life of DDR4 modules using CXL controllers rather than letting them become obsolete as servers migrate to DDR5-only platforms.

Meta reported efficiency gains of as much as 25% in server count on some inference workloads across millions of servers, while average latency dropped about 29% on distributed cache systems.

However, the workaround did not succeed with every memory chip. Meta said off-the-shelf CXL products bundle controllers with DRAM, which blocks reuse of existing DDR4 stockpiles. Those stacks also caused expansion memory to run roughly ten times slower on bandwidth and about 60% higher on latency than directly attached DRAM.

Meta's answer was its in-house Vistara ASIC, a model specifically built to be reused, with power efficiency and low latency advantages designed in. The company also pairs the ASIC with software that monitors workloads and switches it off when unacceptable delays are detected.

Memory chip prices are through the roof

Memory chip prices keep climbing, with the trajectory steepening as the AI buildout absorbs everything manufacturers can produce. Counterpoint Research reported an 80% to 90% quarter-over-quarter price increase in Q1 2026.

Marvell's estimate came in at 90% to 95% single-quarter increases for conventional DRAM, with hyperscalers expected to spend roughly 30% of their budgets on memory in 2026, up from about 8% in 2023 and 2024. That shift matters beyond the data center: conventional DRAM is also the memory used in PCs, laptops, and consumer electronics, so tight supply and record contract prices feed through into broader hardware costs.

TrendForce expects another 13% to 18% quarterly rise in conventional DRAM contract prices in the third quarter of 2026.

No fast relief in sight

Supply is not catching up soon. As Cryptopolitan reported, China's ChangXin Memory Technologies has hit a capacity ceiling near 240,000 wafers a month, constrained by US export controls and yields that Counterpoint estimates run 42% below Samsung and SK Hynix. SK Hynix has committed about $38 billion to two new fabs, but its Y2 DRAM plant is not expected to reach the cleanroom stage until mid-2029.

The pressure could intensify before more silicon arrives. Two unions representing about 10,000 Micron workers in Taiwan are weighing a strike vote in September over how bonuses are calculated, Cryptopolitan reported. Micron is one of three firms that control roughly 94% of the DRAM market, and a stoppage at its Taiwan fabs — which cannot be relocated quickly — would tighten a market that SK Hynix chief Kwak Noh-Jung expects to remain short until the end of 2030.

The length of that timeline is why workarounds like DDR4 recycling and CXL pooling are drawing attention: with new fabs years away and the market concentrated in three suppliers, extending the life of installed memory is one of the few levers buyers can pull in the near term.

Source: Cryptopolitan, Wccftech, EE Times, Counterpoint Research, Tom's Hardware