KAIST student wins best paper honor at international symposium
Key Takeaways
- •Lee Jung-hyun, a KAIST TERA Lab graduate student, received the Best Student Paper — Honorable Mention at the 2026 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity held in Dallas, Texas.
- •His award-winning paper applied Tucker decomposition to compress power distribution network data by approximately 695 to 1 in a 256-port test while preserving reconstruction accuracy.
- •The tensor-based method targets power delivery and signal integrity challenges in densely integrated semiconductor packages including high-bandwidth memory and chiplet systems.
- •The IEEE symposium, held annually since 1959, is a leading international conference that draws 1,500 to 2,000 engineers and researchers from industry, academia, and government institutions.
- •KAIST TERA Lab, led by professor Kim Joung-ho, focuses on high-speed semiconductor packaging, signal and power integrity, and next-generation memory architectures including HBM.
Business
Tech & Science
KAIST student wins best paper honor at international symposium
Published Aug. 13, 2026, 11:42 a.m. KST
Lee Jung-hyun / Courtesy of Korea Advanced Institute of Science & Technology TERA Lab
Lee Jung-hyun, a graduate student at the Korea Advanced Institute of Science & Technology (KAIST) TERA Lab, received the Best Student Paper — Honorable Mention at the 2026 Institute of Electrical and Electronic Engineers International Symposium on Electromagnetic Compatibility, Signal & Power Integrity, the semiconductor research group said Thursday.
The symposium was held from Aug. 3 to 7 in Dallas, Texas. Lee was recognized for his paper, “Physics-Aware Tensor Learning for Data-Efficient Multi-Port Power Distribution Network Analysis.”
The paper introduced a new tensor-based method for efficiently storing and analyzing large volumes of power distribution network (PDN) data generated in advanced semiconductor packages such as high-bandwidth memory (HBM) and chiplet systems. Ensuring stable power delivery across hundreds of ports in these densely integrated packages is a growing challenge for the semiconductor industry, as surging demand for AI accelerators pushes manufacturers toward ever-larger HBM stacks and more complex multi-die designs where signal and power integrity directly affect performance and reliability.
By using a mathematical technique called Tucker decomposition to extract representative patterns from the data, the research team achieved a compression ratio of about 695 to 1 in a test involving a 256-port PDN, while maintaining the targeted reconstruction accuracy.
“I became interested in tensors while studying how artificial intelligence and supercomputers process high-dimensional data, and applied an idea that emerged from that process to signal integrity and power integrity problems in this research,” Lee said.
“Going forward, I hope to verify the accuracy and interpretability of tensor-based representations in more realistic semiconductor package structures.”
The symposium is one of the world’s leading international conferences on electromagnetic compatibility, signal integrity and power integrity. Held annually since 1959, it brings together about 1,500 to 2,000 engineers and researchers from industry, academia and government institutions.
KAIST TERA Lab is a research group focused on high-speed semiconductor packaging, signal and power integrity, and next-generation memory architectures including HBM and high-bandwidth flash. The group is led by professor Kim Joung-ho, who is known for introducing the fundamental concept, design and architecture of HBM.
