Samsung Electronics is showcasing two concept architectures that it describes as industry firsts — a 3D-stacked high-bandwidth memory design called zHBM and a NAND flash solution dubbed zNAND-O — at Future of Memory and Storage 2026, held from Tuesday through Thursday at the Santa Clara Convention Center in California. The concepts arrive amid intensifying competition among the three major memory makers — Samsung, SK Hynix, and Micron — to supply HBM for AI accelerators from companies including NVIDIA and AMD, where memory bandwidth has become a defining constraint on system performance.

The zHBM architecture positions high-bandwidth memory directly on top of AI processors rather than placing HBM packages alongside GPUs and other accelerators on the same plane, as conventional designs do. By reducing the physical distance that data must travel, Samsung says the shorter connection could increase bandwidth while lowering power consumption, easing data bottlenecks in AI systems where processors continuously exchange large volumes of information with memory. The approach targets the longstanding industry challenge known as the "memory wall," where data transfer between processors and memory has not kept pace with improvements in processing speed.

According to Samsung, a next-generation interface system incorporating zHBM could deliver up to eight times the performance of HBM5, the eighth-generation HBM standard. Energy efficiency could improve by as much as threefold. The company also said advanced wafer bonding technology could cut thermal resistance by more than half compared with HBM5, addressing one of the principal challenges of vertically stacking high-performance memory and processors. Through-silicon vias (TSVs), already used in current HBM packages to vertically connect DRAM dies, are central to existing stacked-memory manufacturing and would be extended further under the zHBM concept.

The architecture can be tailored to individual AI systems through an interlayer between the memory and accelerator that incorporates customer-specific intellectual property. Depending on system design, this interlayer could be configured to expand memory capacity or enhance processor performance. Samsung said it plans to collaborate with customers to optimize the connection between their AI processors and memory and further refine zHBM performance. The company did not disclose a commercialization timetable.

Samsung is also extending its 3D memory approach to NAND flash with zNAND-O, which remains under development. The solution combines Samsung's V-NAND stacking technology with through-silicon vias (TSVs), stacking four or eight semiconductor dies vertically into a single package. The "O" in the name denotes its focus on on-device AI, where data is processed locally rather than transmitted to an external server. By stacking the dies, Samsung aims to reduce the space occupied by memory while improving data-loading bandwidth and response times, targeting devices that must process large volumes of data locally and in real time. On-device AI processing has gained traction as device makers seek to reduce latency, lower cloud-dependency, and address data privacy concerns.

At the same event, Samsung unveiled V10 BV-NAND, its 10th-generation V-NAND technology featuring more than 400 vertically stacked memory-cell layers — making it the industry's first V-NAND design to surpass the 400-layer mark, according to the company. The higher-density structure allows more memory cells to be placed within the same area, increasing storage capacity while improving performance and power efficiency. Rival NAND manufacturers including SK Hynix, Micron, and China's YMTC have also been racing to increase vertical layer counts in their respective 3D NAND technologies.

The announcement comes 13 years after Samsung introduced what it described as the world's first V-NAND technology at the same industry event. Samsung plans to leverage these new 3D memory technologies to address growing demand for high-performance computing and AI infrastructure.