Samsung Electronics unveiled its next-generation AI memory portfolio at the Future of Memory and Storage (FMS) 2026 conference in Santa Clara, California, presenting a technology roadmap designed to address the rapidly growing demands of high-performance computing and artificial intelligence infrastructure.

The company displayed about 30 memory and storage technologies at an AI cloud server-inspired booth. Jin-Yub Lee, Executive Vice President and Head of Flash Product & Technology, and Kyungryun Kim, Vice President of the DRAM Design Team, delivered the opening keynote, titled “Driving the Wave of AI Revolution: 3D Innovations in Memory & Storage Architecture.”

Vertical architectures aim to reshape memory-processor integration

At the center of Samsung’s roadmap are two concept models that significantly alter how memory connects with processors. The company introduced zHBM, which stacks high-bandwidth memory vertically above AI accelerators rather than placing it beside the chip. Samsung said the approach shortens the data path and delivers roughly eight times the performance of HBM5, more than ten times the memory density, and three times the energy efficiency, while cutting thermal resistance by more than half.

The architecture also supports custom intellectual property integration between layers, allowing tailored configurations for specific accelerators. In addition to zHBM, Samsung previewed zNAND-O, a V-NAND-based solution available in four- and eight-layer variants that combines high space efficiency with low latency for real-time edge AI workloads.

Samsung introduces V10 BV-NAND and details production roadmap

Samsung also announced V10 BV-NAND, which it described as the industry’s first Bonding V-NAND architecture enabled by new wafer bonding technology. The device has more than 400 layers and increases memory density by about 58 percent compared with the previous V9 generation, while also improving read, write and I/O performance. Samsung said the milestone comes 13 years after it introduced the industry’s first V-NAND.

Beyond concept hardware, Samsung outlined its near-term production plans. After what it described as the industry’s first mass production of HBM4 in February, the company began shipping HBM4E samples in May and displayed its HBM5 model at FMS 2026. Samsung also showcased LPDDR5X-PIM, which it described as the industry’s first low-power DDR memory with processing-in-memory technology. The system performs computations within the memory array to reduce data movement and power consumption, a design approach that is becoming more relevant as AI systems push memory bandwidth and efficiency requirements higher.

For data center infrastructure, Samsung highlighted its PM1763 and BM1773 enterprise storage solutions. The company said that, as the only integrated device manufacturer with leading capabilities across memory, foundry and advanced packaging, it is promoting an end-to-end turnkey strategy that combines design and manufacturing services to shorten development cycles and improve performance for AI semiconductor customers.