Synopsys, Inc. (SNPS) shares fell 1.63% to $394.68 as the company unveiled a major 3D PCIe 6.0 milestone. The demonstration brings high-speed PCIe connectivity into stacked-die designs built for demanding computing systems, and Synopsys said the advance is aimed at supporting faster AI chips, high-performance computing (HPC) platforms, storage products, and data center infrastructure.

The company validated 64 GT/s PCIe 6.0 performance in a new stacked-die design. The 3D architecture targets AI accelerators, HPC systems and major data centers. Synopsys says the design supports higher bandwidth, lower latency and efficiency, and the milestone extends its PCIe expertise into advanced multi-die packaging.

Synopsys Advances 3D PCIe 6.0 Connectivity

Synopsys demonstrated PCIe 6.0 operating at 64 GT/s within a stacked, face-to-face chip architecture. The design delivered bandwidth reaching 128 GB/s through an eight-lane configuration using PAM4 signaling. That data rate is the defining feature of the PCIe 6.0 standard, which industry standards body PCI-SIG finalized in January 2022 as a doubling of PCIe 5.0's 32 GT/s rate, with PAM4 signaling as one of its key enablers. The test therefore moved PCIe connectivity beyond conventional two-dimensional chip layouts.

The company used a 5-nanometer PCIe 6.0 PHY adapted for three-dimensional integrated circuit (3D IC) technology. Synopsys built the test chip from an existing PCIe 6.0 implementation and added the changes needed for stacked dies. Silicon testing confirmed that the technology operated successfully after packaging, startup, and measurement.

The demonstration also showed receiver performance exceeding PCIe 6.0 bit-error requirements by wide margins. In addition, the architecture shortened the connections between separate dies compared with traditional side-by-side packaging. This structure can support higher bandwidth, reduced latency, improved signal integrity, and greater computing density.

3D Packaging Targets AI and Data Center Systems

Modern AI processors increasingly combine specialized functions across several dies instead of relying on a single large chip. As a result, chip designers need faster links between computing, memory, networking, and storage components. Synopsys positioned its latest demonstration as one option for meeting those growing connectivity demands. The industry has also organized around dedicated die-to-die standards such as UCIe (Universal Chiplet Interconnect Express), a consortium-backed specification introduced in 2022, giving chipmakers a broader set of interconnect options for multi-die designs alongside long-established PCIe links.

The technology can support AI accelerators, high-performance processors, SmartNICs, DPUs, storage controllers, and data center switches. It can also support systems using Compute Express Link (CXL) connectivity for memory and accelerator expansion. With the demonstration, Synopsys is extending existing interface technology toward more complex multi-die platforms.

Three-dimensional packaging creates technical challenges because engineers must manage electrical behavior across stacked components. Synopsys addressed TSV placement, die interaction, inductors, signal performance, and full-stack modeling during the development process. The company also worked to limit unnecessary TSV additions while maintaining PCIe 6.0 performance.

Synopsys Builds on Long PCIe Development History

Synopsys has developed PCIe technologies for more than two decades across several generations of the standard. Its portfolio includes PHY technology, digital controllers, security components, verification systems, and interoperability testing tools. The company has supported about 4,000 customer tape-outs across seven PCI Express generations, and it has long ranked among the world's largest suppliers of semiconductor interface IP by revenue.

The latest project links that established PCIe portfolio with the semiconductor industry's shift toward multi-die architectures. Synopsys combines its electronic design software with interface technologies for advanced packaging and heterogeneous integration. These tools support architecture planning, package optimization, software development, system validation, and manufacturing analysis.

The milestone also strengthens Synopsys' position within the expanding market for advanced semiconductor packaging. AI and HPC systems continue requiring greater bandwidth while power and physical space remain major design constraints for chipmakers. Synopsys now offers a validated PCIe 6.0 path designed specifically for emerging three-dimensional chip architectures. Standards work is continuing in parallel: PCI-SIG has already begun developing a PCIe 7.0 specification targeting 128 GT/s, and interface IP of the kind Synopsys just validated typically reaches end products only after customers complete their own multi-year chip designs, placing today's demonstration within a longer technology pipeline.

Source: Blockonomi