Designing a cutting-edge chip currently takes between 18 and 30 months from first sketch to fabricated silicon. Jeff Dean, former Chief Scientist at Google, believes artificial intelligence can compress that timeline to as little as three months.

The claim, made during an appearance on the Dwarkesh Podcast in February 2025, rests on a straightforward observation: most of the 18-to-30-month window is consumed by human engineers making design decisions that could, in theory, be automated. Actual fabrication at a foundry such as TSMC — the Taiwan Semiconductor Manufacturing Company, which manufactures chips for many of the industry's designers — takes only about four months. The remainder is spent refining floor plans, deciding where each functional block sits on the silicon, routing the wires that connect them, and running simulations to verify the design. Dean's thesis is that reinforcement learning, a technique in which software learns through trial and feedback rather than explicit rules, and improved electronic design automation (EDA) tools — the software toolchains engineers use to lay out and verify chip designs — can shrink the human-intensive design phase from over a year to just a few months, and with a smaller team.

From AlphaChip to Production Silicon

Dean's argument is grounded in years of research at Google, most notably the AlphaChip system detailed in a paper published in the journal Nature in June 2021. AlphaChip used reinforcement learning to automate chip layout, a task that typically occupies teams of engineers for weeks. The system generated layouts in under six hours that matched or surpassed the quality of human expert work.

The technology was more than a lab demo. AlphaChip was deployed in production designs for Google's Tensor Processing Units, the custom AI accelerators that power much of the company's machine learning infrastructure.

Dean argued that shorter design cycles would reduce the need for engineers to predict where AI research will stand 18 months into the future. Instead, teams could design chips tailored to current algorithmic needs and iterate quickly as those needs evolve, rather than committing to specifications more than a year ahead of fabricated silicon.

The Industry Is Already Moving

Dean's vision is no longer purely theoretical. Several have begun demonstrating what AI-assisted chip design looks like in practice.

Architect Labs announced in September 2026 that it had designed an inference chip called Redwood, moving from specification to proof-of-concept in under two weeks — different start and end points from the sketch-to-fabricated-silicon benchmark Dean described.

OpenAI has also entered the hardware space. Its Jalapeño AI accelerator went from initial architecture to first silicon in under 20 months, with the critical RTL-to-tape-out phase — from register-transfer-level design code to the finished layout handed off for fabrication — completed in nine months. That end-to-end figure is at or below the fast end of the traditional 18-to-30-month window Dean cited, though it remains far above the three-to-six-month range he argues is possible. The company used large language models to assist in the design process, achieving a 10% reduction in chip area compared to equivalent human designs — a metric that matters because die area shapes how many chips can be produced from each silicon wafer.

Dean himself left Google in mid-2026 to co-found Discovery Loop alongside other researchers. The company's focus is building systems for recursive self-improvement in hardware design automation. Taken together, these early results — two-week proof-of-concept sprints, 20-month silicon timelines, and reinforcement-learning layout tools — give the industry a set of reference points against which future claims about AI-compressed design cycles can be measured.