Cadence introduced Maestro on October 26, giving chipmakers a suite of domain-specialized AI models that can be fine-tuned on proprietary design data and operated entirely behind corporate firewalls, according to the company's announcement. The launch also sharpened the strategic question at the heart of its rivalry with Synopsys: who controls the models, the data they process, and the value they generate?

Two bets on where the models live

Cadence and Synopsys are the industry's two leading vendors of electronic design automation (EDA) software — the tools chipmakers rely on to design and verify silicon — so their competing visions for where AI models run carry weight well beyond their own product lines.

Maestro packages specialized models with NVIDIA's open-weight Nemotron technology, reinforcement learning, and Cadence AI Super Agents wired into chip-design tools. Customers can host the full stack on their own servers, run it through Cadence, or place it in secured public clouds, and Cadence said it is collaborating with NVIDIA on OpenShell security integration. For customers, that choice is not merely infrastructural: because the models are fine-tuned on proprietary design data, where the stack runs also determines where those sensitive layouts reside.

"There are more (AI) model providers out there than there are (chip design software) vendors."

Cadence senior vice president Paul Cunningham told Reuters that open- and closed-weight approaches were being "pursued equally."

Synopsys has charted the opposite course. Under its September 30 partnership with OpenAI, GPT-Synopsys will run on OpenAI-hosted infrastructure and plug directly into Synopsys design tools, with revenue split between the two companies. Synopsys has pledged encryption, adjustable data-retention controls, and a commitment not to train on customer data. Even so, the divide is not absolute: the company's wider Autopilot strategy also allows agents to be integrated into customers' own AI platforms.

The efficiency claim, unverified on total cost

According to Cadence, Maestro produced results up to 30% higher in quality and used tokens five times more efficiently than a general-purpose model in early workflows, with its engineering tools checking agent outputs against design constraints and feeding the results back into training. These are the company's own figures, though, and savings across a full design project have not been independently verified.

As Cryptopolitan has previously reported, the cost per completed task matters more than the sticker price of tokens when a model needs repeated attempts or engineers have to repair its output. Housing Maestro on-premises may shield sensitive layouts, but the infrastructure itself carries real costs. The first models are slated for select early-access customers in the fourth quarter of 2026, and those deployments will offer the first real-world read on the efficiency claims — and on which hosting arrangement customers actually choose.

A market big enough to fight over

The prize is considerable. SEMI data show the electronic system design market generated $5.71 billion in revenue in the second quarter of 2026, up 12.2%, with semiconductor IP revenue growing 20.4% and IC physical design and verification rising 16.6%. TrendForce forecasts nearly 31% growth in AI server shipments this year as Google and Amazon expand custom-chip programs — and every new custom-chip program adds to the design and verification workload that EDA tools like these serve.

Cadence, for its part, unveiled a sovereign AI data center in Munich on October 21, as it announced, addressing demand to keep sensitive workloads within regional borders.

The company posted third-quarter revenue of $1.633 billion, up 22%, with an $8.2 billion backlog and a 21% full-year revenue-growth outlook, per its earnings release. Its AI Super Agents have more than 100 active customer engagements. Reuters reported that shares rose 3.9% after the Maestro announcement.

That is where the rivalry will ultimately be decided: not by token counts or cloud promises, but by whether engineers can produce better chip designs faster without inflating the total bill.