ASE Targets Q1 2027 Initial Production for AMD Venice Panel-Level Packaging

ASE Technology Holding has put panel-level packaging hardware built for Advanced Micro Devices' next-generation Venice server processor on display at the Open Compute Project (OCP) summit, with initial production targeted for the first quarter of 2027.

The display was highlighted by the semiconductor research firm SemiAnalysis, which covered the demonstration at the OCP Global Summit, the annual data-center hardware event organized by the Open Compute Project Foundation and held in San Jose, California. The OCP Global Summit is where data-center operators and the suppliers of their hardware converge, making it a venue where a back-end manufacturing step like packaging becomes visible to the companies that will ultimately deploy the processors.

A Shift From Wafers to Panels

Panel-level packaging is an advanced chip assembly technique that processes semiconductors on large, rectangular panels instead of conventional circular wafers. Because rectangular panels make use of more available area than round wafers, the approach is considered better suited to large processors and chiplet-based designs, offering improved area utilization and the potential for lower per-unit packaging costs as device sizes grow.

For large, chiplet-based server processors — the category the technique targets — the packaging step is where the individual pieces of silicon come together. ASE's initial production target puts that readiness on a concrete timeline, aligning a new packaging format with a processor generation that also debuts on a new manufacturing node.

AMD's Venice Server Generation

Venice is the next generation of AMD's EPYC server processor family, following the Turin generation. AMD has publicly identified Venice as its first product family to be manufactured on Taiwan Semiconductor Manufacturing Company's 2-nanometer process, placing its assembly and packaging under close industry scrutiny as the platform moves toward production.

The convergence is notable: Venice pairs a first-ever 2-nanometer EPYC manufacturing node with a shift to panel-based assembly, and the public OCP demonstration offers a preview of that packaging stage well before the first-quarter 2027 initial production target arrives.

About the Companies

ASE Technology Holding, headquartered in Taiwan, is the world's largest provider of outsourced semiconductor assembly and testing (OSAT) services, supplying packaging and test capabilities to chip designers across computing, communications, and consumer segments. Its decision to showcase Venice-specific panel-level packaging hardware at OCP underscores the role of packaging partners in bringing next-generation server processors to market.

This content was first published on COINOTAG: https://en.coinotag.com/ase-amd-venice-panel-level-packaging-q1-2027